This invention relates to the field of solid state electronics and, more particularly, to integrated circuitry for digital logic applications.
The current trend in digital electronics is to incorporate increasingly greater circuit complexity on a single semiconductor circuit chip. Considering the military applications presently under development, for example, the electronics specifications for a variety of missions include a requirement for very large scale integration (VLSI), i.e., greater than 10,000 gates on a single integrated circuit chip. Complexities in the VLSI range, however, impose a number of limitations on chip design.
The principal requirements of a digital integrated circuit technology compatible with ultra-high speed large scale (LSI) and very large scale (VLSI) integration are very high density (i.e., a small amount of chip area for each gate), low gate power dissipation, extremely low dynamic switching energy (normally expressed as the speed-power product P.sub.D .tau..sub.D), high speed (a very low signal propagation delay through each gate), and a very high yield for the chosen circuit fabrication process. These requirements arise because large numbers of gates, in the 10.sup.4 to 10.sup.5 range, cannot be placed on a reasonably sized chip (approximately 1 square centimeter in area) unless the area of each gate is small, i.e., less than approximately 1000 .mu.m.sup.2 /gate. Moreover, the power consumed by each gate must be well below 1 mW if the total power dissipation for the chip is to remain at a manageable level. The constraint on dynamic switching energy is especially severe for high speed VLSI because the chip power dissipation limit must be maintained at high clocking frequencies. Assuming, for example, a maximum power dissipation of 2 watts for a semiconductor chip containing 10.sup.4 gates at an average gate clocking frequency of 1 GHz, the maximum allowable gate dynamic switching energy P.sub.D .tau..sub.D is 0.1 pJ.
Historically, the development of monolithic integrated circuit technology has been almost exclusively concerned with devices based on silicon materials. With respect to the overall functional complexity which has been achieved on a silicon chip in medium speed logic, and considering the cost per gate which has been reached for such chips, the improvements which have been attained in silicon integrated circuit (IC) technology have been remarkable. In other areas, however, such as the maximum switching speed of silicon ICs, progress has been more limited. Because of such limitations, an attractive alternative available for developing superior high speed LSI and VLSI circuitry is to replace silicon with another semiconductor having superior electron properties. Gallium arsenide (GaAs), for example, is capable in principle of being fabricated into virtually all the device structures which have been achieved in silicon. GaAs differs from silicon principally in its energy band structure, the structure of gallium arsenide resulting in a high (five times that of silicon) electron mobility. This electron mobility, in conjunction with the availability of a semi-insulating GaAs substrate (which cannot be obtained in silicon technology), provides the basis for the development of GaAs integrated circuits which will operate at significantly higher switching speeds and with much lower dynamic switching energy than conventional, silicon-based devices.
Initial progress in GaAs device research was slow, primarily due to the unavailability of an effective method for controlling the active layers of the devices. More recently, however, GaAs integrated circuit technology has overcome such difficulties and advanced considerably, due in large part to the emergence of a viable ion implantation technology and to the fabrication improvements which have been made in microlithography pattern replication techniques. A high-yield planar fabrication approach has been developed, for example, which capitalizes on the proven uniformity, reproducibility, and low cost of implanting directly into semi-insulating GaAs to form the active layers of a device. Planar circuits have been fabricated by using multiple localized ion implants, thereby permitting the active layers of both Schottky diodes and field effect transistors (FETs) to be individually optimized on the same device. A planar metal semiconductor field effect transistor (MESFET) may be fabricated with two implants--a shallow, lightly doped n.sup.- implant forming the channel region, and a deeper n.sup.+ implant forming the source and drain regions. In this manner, self-aligned gates with a length of approximately 1 .mu.m, requiring approximately 0.75 .mu.m alignment accuracy, may be formed and will exhibit excellent device characteristics. A thin dielectric cap, through which the implantations are made, is utilized for most implantation annealing to protect the GaAs surfaces during processing and to passivate the surface.
Inasmuch as GaAs Schottky barrier diodes are among the fastest switching semiconductor devices available and their switching energy (approximately 10.sup.-15 J) and required area (the active area can be as small as 1 .mu.m.times.2 .mu.m) are very low, their use as logic elements in GaAs digital ICs is very desirable. A logic circuit approach has been developed utilizing high conductance, low capacity Schottky switching diodes as the primary nonlinear logic elements, with inversion and gain accomplished by GaAs depletion mode Schottky gate MESFETs. This Schottky diode FET logic (SDFL) approach, which is disclosed in detail in U.S. Patent Application Ser. No. 011,266, filed Feb. 12, 1979, and now U.S. Pat. No. 4,300,064, exhibits major savings in chip area as compared to previous approaches in which FETs have been used as the primary logic elements.
The SDFL approach for digital integrated circuits incorporates as its basic structure the single level SDFL NOR gate. This gate uses a group of diodes to provide the positive NOR function and an FET to provide inversion and gain. By means of multi-gate or series FETs, the basic SDFL circuit can be extended to two-level OR/NAND functions or, using "drain-dotting", to OR/NAND/WIRED-AND three-level logic functions. In general, however, the number of terms which can practically be "NANDed" with series FETs in SDFL is limited, due to parasitic gate capacitances and FET "ON" resistances, to two or perhaps three without substantial performance degradation. Somewhat similar restrictions apply to the number of "drain dot" terms (i.e., parallel FETs sharing the same pull up element) before the interconnect and drain capitance parasitics slow circuit speeds. This fan-in restriction impedes the effective implementation of logic functions with these gates, causing penalties both in the number of gates (complexity) and the amount of logic propagation delay (speed) required to achieve a desired function.
Consequently, a need has arisen for an integrated logic circuit which exhibits low power, high speed, and very high functional complexity, such as a general two level gate with essentially unlimited fan-in at both levels of logic. With such a gate, any combinatorial logic function may in principle be implemented with a single gate and one logic propagation delay from the application of the inputs and their complements.